Saturday, 2 June 2012

Transistor Circuits

Transistor Behavior

The Ebers-Moll equation describes the relationship between the collector current $I_C$ and the voltage drop from base to emitter $V_{BE}$ by

\begin{displaymath} I_C = I_o (e^{\frac{eV_{BE}}{kT}} - 1) \end{displaymath} (3)
where $I_o$ is the reverse leakage current from the emitter to the base, $e = 1.6 \times 10^{-19}$ C is the elementary unit of charge, $k = 1.38 \times 10^{-23}$ J/K is the Boltzmann constant, and $T$ is the absolute temperature (in Kelvin). With typical doping levels, the leakage current arising from the ``intrinsic'' behavior of the pure semiconductor is very small, and the second term (-$I_o$) is negligible, giving a simple exponential dependence of $I_C$ on $V_{BE}$.

Assignment

Figure 13: A circuit for measuring the current voltage relationship of an npn junction transistor (for testing the Ebers-Moll equation).
\includegraphics{lab3-ebersmoll.eps}

  1. Construct the circuit of Figure 13. The 5 k$\Omega $ potentiometer acts as a variable voltage divider allowing you to vary the voltage across the base emitter junction. The Ebers-Moll equation suggests an exponential dependence of the current flowing from the collector to the emitter on $V_{BE}$. Measure the voltage drops across the 100 $\Omega $ and 1 k$\Omega $ resistors to deduce $I_C$ and $I_E$ for various values of $V_{BE}$. Note that $V_{BE}$ is not the voltage drop from the base to ground in this circuit. Start with small values of $V_{BE}$, and do not allow $I_C$ or $I_E$ to exceed 5 mA.
  2. Using your data, produce a graph of $ln(I_C)$ vs. $V_{BE}$, and compare it with the behavior predicted by the Ebers-Moll equation.
  3. Use the Ebers-Moll equation and your data to determine values of the leakage current $I_o$ and the temperature of your transistor. Comment on whether you think the Ebers-Moll equation is a good model.
  4. Also use your data to determine an approximate value of $\beta = \frac{I_C}{I_B}$ for your transistor. The base current is simply $I_B = I_E - I_C$.


Transistor Switch


Figure 14: Transistor switch circuit.
\includegraphics{lab3-switch.eps}
The circuit shown in Figure 14 implements a transistor as a switch controlling power delivered to the ``load'' $R_C$. With a proper choice of $R_B$, closing the mechanical switch drives a large enough base current that the current flowing through the collector resistor forces the voltage of the collector below that of the base. That is, the collector current produces a voltage drop across $R_C$ of about 5 V. The collector voltage is very close to the emitter (ground in this case), and the right branch of the circuit behaves as if the collector is grounded. In this state, called saturation, increasing the base current can produce no further increase in the collector current, because $R_C$, not the transistor, is limiting the current. The Ebers-Moll equation and the rough rule $I_C = \beta I_B$ do not apply here. Opening the switch brings $V_{BE}$ below 0.6 V, and the transistor shuts off power to the load.
In designing the circuit, let us assume that $R_C = 1$ k$\Omega $. (Perhaps we know that this is the resistance of the load we would like to switch, or perhaps we want to limit the collector current to $5\textrm{V}/1\textrm{k}\Omega = 5$ mA.) Within these constraints, we need to choose an appropriate value of $R_B$ to produce the behavior outlined above. Assuming $\beta = 100$ for the transistor, we need a base current of at least 0.05 mA to saturate the transistor and drive maximal current through $R_C$. The maximal value of $R_B$ is then $5\textrm{V}/0.05\textrm{mA} = 100$ k$\Omega $. However, it is important to be conservative, because we cannot depend on a particular $\beta$ value. A transistor operating in saturation is not sensitive to excess base current, so we can safely use a base resistor much smaller than our upper limit.

Assignment

  1. Construct the circuit of Figure 14 using $R_C = 1$ k$\Omega $ and $R_B = 10$ k$\Omega $.
  2. Verify that the circuit behaves as advertised in the above design discussion. That is, measure the voltage drops across $R_B$ and $R_C$ with the switch in ``on'' and ``off'' positions. Also measure the voltage difference between the collector and emitter in these two states. Comment on your observations.


Logical NOT Gate


Figure 15: Logical inverter (NOT gate) circuit.
\includegraphics{lab3-inverter.eps}
The circuit of Figure 15 is identical in form to the switch circuit of Section 3.2, except that we consider the behavior of the circuit as a logic gate with input and output terminals labelled with $V_{in}$ and $V_{out}$ in the figure. When $V_{in}$ is above about 0.6 V, the base current turns on, significant current flows through $R_C$, and $V_{out}$ drops. Conversely, when $V_{in}$ drops below 0.6 V, the base and collector currents are zero, the voltage drop across $R_C$ is zero, and $V_{out}$ is 5 V. Hence, this circuit inverts its input, at least in the crude sense that when $V_{in}$ is high, $V_{out}$ is low and vice versa.

Assignment

  1. Construct the circuit of Figure 15 using $R_C = 1$ k$\Omega $. Produce a graph of $V_{out}$ vs. $V_{in}$ covering values of $V_{in}$ in the range 0-5 V for both $R_B = 10$ k$\Omega $ and $R_B = 100$ k$\Omega $.
  2. The TTL (Transistor-Transistor Logic) digital logic standard assigns voltages in the range 0-0.8 V the value 0 or ``false'' and voltages in the range 2.0-5 V the value 1 or ``true.'' Drive the circuit with a square pulse signal alternating between 0 V and 5 V (not between -2.5 V and +2,5 V). You will need to use the DC offset knob on the function generator to produce this signal. Based on this observation and your graph of the transfer function of the circuit, comment on the extent to which this device behaves like a logical inverter, or NOT gate, with the truth table:
    $V_{in}$ $V_{out}$
    0-0.8 V ``false'' 2.4-5 V ``true''
    2.0-5 V ``true'' 0-0.4 V ``false''
    Which of the two values of $R_B$ is better for this application? Explain.
  3. Construct Spice simulations for comparison with your measurements. You will need to include the following .MODEL statement for a generic npn bipolar junction transistor (with $\beta = 100$) in your circuit file. 
    .MODEL Qnpn NPN(BF=100)
    You can then specify transistors with statements of the form
    [Name] [C] [B] [E] Qnpn
    where the [C], [B], and [E] entries identify the collector, base, and emitter nodes, respectively.


Common Emitter Amplifier

Transistors are used in amplifiers that amplify voltage and current. Our first amplifier is a voltage amplifier called a common emitter amplifier for which a change in input voltage $\Delta V_{in}$ leads to a change in output voltage $\Delta V_{out}$ linearly proportional to $\Delta V_{in}$,
\begin{displaymath} \Delta V_{out} = A_v \Delta V_{in} \end{displaymath} (4)
where $A_v$ is a constant called the voltage gain.

The basic circuit


Figure 16: Common emitter amplifier.
\includegraphics{lab3-ceamp1.eps}
Consider the circuit of Figure 16. The values of the resistors $R_1$, $R_2$, $R_C$, and $R_E$ are chosen so that $V_{out}$ is about 7.5 V (centered in the 0-15 V range) and $V_{in}$ is about 0.6 V above the emitter, ensuring that a current always flows from the collector to the emitter, regardless of whether we are exciting the circuit. This is called the quiescent state, or the DC operating point, of the circuit.
If we apply a change in voltage $\Delta V_{in}$ to the input, this change is mirrored by the emitter. To see this, remember that the transistor is ``on'' and so the emitter voltage stays about 0.6 V below the base. We have $\Delta V_E = \Delta V_{in}$, leading to a change in the emitter current $\Delta i_E = \Delta V_{in}/R_E$. The collector and emitter currents are approximately equal, since $\beta \approx 100$, so we find

\begin{displaymath} \Delta V_{out} \approx -\Delta i_E R_C = \frac{R_C}{R_E} \Delta V_{in} \end{displaymath} (5)
giving a voltage gain of
\begin{displaymath} A_v = -\frac{R_C}{R_E}. \end{displaymath} (6)
The minus sign comes in, because an increase in current through $R_C$ lowers the collector voltage.

$\beta$ independent behavior

Note that the behavior of the circuit does not depend on the $\beta$ value of the transistor. That is, we rely on the fact that the exponential dependence of $i_C$ on $V_{BE}$ ensures that the transistor can supply (more than) enough current to follow changes in the base voltage. An important design consideration is that we must not saturate the transistor.

Why not $R_E = 0$?

Equation 6 might inspire the question ``What happens if we remove the emitter resistor $R_E$? Do we get infinite gain?'' It turns out that we get maximal gain, but that the intrinsic dynamic resistance $r_e = \frac{dV_{BE}}{dI_E}$ of the emitter-base junction, looking at the base from the emitter, limits the gain to a finite value. Using the Ebers-Moll equation (Equation 3), we find
\begin{displaymath} r_e = \frac{kT/e}{I_E} \approx \frac{kT/e}{I_C}. \end{displaymath} (7)
At room temperature this gives something like $r_e \approx 25/I_C$ for $I_C$ in mA and $r_e$ in $\Omega $. In fact, you measured a value of $kT/e$ for your transistor in Section 3.1. If $R_E = 0$, then the voltage gain becomes
\begin{displaymath} A_v = -\frac{R_C}{r_e} \approx -\frac{I_C R_C}{kT/e} \end{displaymath} (8)
which introduces two unwanted visitors - dependence on both temperature and collector current. The first leads to temperature instability, and the second leads to nonlinear gain. We avoid these problems by using a large enough emitter resistor $R_E$ that the emitter voltage is insensitive to changes in the intrinsic emitter resistance $r_e$.

A refined circuit


Figure 17: AC common emitter amplifier with capacitive coupling on the input and output.
\includegraphics{lab3-ceamp2.eps}
The circuit of Figure 17 includes some refinements over that of Figure 16. If we only wish to amplify time dependent signals, we couple the input and output signals to the circuit with capacitors $C_1$ and $C_2$. This capacitive coupling removes DC components from the input and output that might interfere with the DC operating point of the amplifier. These coupling capacitors form high pass filters with the input and output impedances. Their values should be chosen so as to transmit signals of interest. The capacitor labeled $C_E$ is chosen to bypass the emitter resistor at signal frequencies. You will investigate the effect this has on the gain. The bypass capacitor has no effect on the DC behavior of the circuit.

Assignment

Note : In making measurements, use the $\times10$ setting (high impedance) on your oscilloscope probes to minimize loading effects. Remember to compensate your probes.
  1. Design the circuit of Figure 16 for a quiescent collector/emitter current of about 1 mA.5Choose $R_C$ to center the output voltage at 7.5 V. Choose $R_E \approx 20 r_e$ to limit the effects of the variability of $r_e$ on the gain to 5%. $R_E$ together with the quiescent $i_C$ set the emitter voltage. Choose $R_1$ and $R_2$ to place the base 0.6 V above the emitter. This sets their ratio. Then, choose their absolute values to strike a balance between the following two competing concerns. First, we would like the input impedance of the circuit to be as large as possible. Second, the impedance $R_1$ and $R_2$ present at the base should be much smaller than the input impedance at the base. This ensures that the impedance of the ``input source'' is small compared to that of the load it drives. Stated another way, this ensures that enough current flows through $R_1$ and $R_2$ to provide needed changes in base current. The impedance that $R_1$ and $R_2$ present at the base can be determined by deactivating the voltage source and determining their resistance between the base and ground (ignoring the transistor for the moment). The input impedance of the base looks like $R_E$ viewed through the base emitter junction. A small change in base current $\Delta i_B$ produces a large change in the emitter current $\Delta i_E \approx \beta \Delta i_B$ corresponding to a change in emitter voltage $\Delta V_E = \beta \Delta i_b R_E$. Hence, looking into the base has in input impedance $\approx \beta R_E$.
  2. Calculate the input and output impedances (in the Thevenin sense) of your amplifier. Here's a hint for calculating the output impedance. The impedance looking into the collector is huge, because the collector draws a fixed current for a given value of $V_{BE}$. The transistor acts to maintain this current by changing the collector voltage by large amounts if necessary. This last sentence implies a very large collector impedance.
  3. Check your design work by measuring the DC operating voltages of the base and emitter. Are the voltages and quiescent currents what you expect them to be?
  4. Add coupling capacitors $C_1$ and $C_2$ shown in Figure 17. Using your input and output impedances, choose values such that the 3 dB point of the circuit is 100 Hz. Note that these two high pass filters working together yield a lower 3 dB point for the circuit than they give individually. Measure the gain as a function of frequency, producing a graph of your results, and find the 3dB point of the circuit experimentally.
  5. Add the emitter bypass capacitor $C_E$ to the circuit, and observe the effects this has on the gain of the circuit as a function of frequency. That is, produce a gain vs. frequency graph to compare with your graph without the bypass capacitor.6
  6. Check the linearity of your amplifier, both with and without the emitter bypass capacitor, by driving it with a triangle wave form. Any distortion in the output wave form reveals nonlinear gain.

Common Collector Amplifier / Emitter Follower

Our second amplifier circuit is a current amplifier called an emitter follower with a linear voltage gain $A_v$ of approximately one. The output impedance of the circuit is much smaller than the input impedance, while the voltage level is unchanged. Hence, instead of amplifying voltage, this circuit amplifies the current (and power) of the input signal.

Design considerations


Figure 18: AC emitter follower circuit with capacitive coupling on the input and output.
\includegraphics{lab3-efamp.eps}
Consider the circuit of Figure 18. After working with the common emitter amplifier you are likely to have developed some intuition about how to choose values for the resistors and capacitors in this circuit. As with the common emitter amplifier, the DC operating point of the circuit will keep the transistor activated. Changes in base voltage are mirrored at the emitter, because the emitter stays about 0.6 V below the base when the transistor is ``on'' and not saturated. Hence $\Delta V_{out} = \Delta V_{in}$ and $A_v \approx 1$. 7 The value of the emitter resistor $R_E$ is chosen to center the DC output voltage at 7.5 V for the desired quiescent collector/emitter current. The ratio $R_1 / R_2$ is set to place the base 0.6 V above the emitter, and the absolute values are set in the same way as for the the common emitter amplifier (see Section 3.4).

Assignment

Note : In making measurements, use the $\times10$ setting (high impedance) on your oscilloscope probes to minimize loading effects. Remember to compensate your probes.
  1. Construct the circuit of Figure 18. The first design step is to decide on a quiescent collector/emitter current. Without a specific load in mind, an arbitrary choice of $i_C \approx i_E = 1$ mA will get you started. Choose coupling capacitors that give a 3 dB point for the circuit of 100 Hz. Note that these two high pass filters working together yield a lower 3 dB point for the circuit than they give individually.
  2. Check your design work by measuring the DC operating voltages of the base and emitter. Are the voltages and quiescent currents what you expect them to be?
  3. Determine the input impedance by placing a resistor in series with the source and measuring the drop in output voltage. (Think voltage divider.)
  4. Determine the output impedance by measuring the upper 3 dB point of the circuit using the capacitor $C_2$ as the load (in parallel with $R_E$) rather than as a coupling capacitor.


Schmitt Trigger

Typical ``real world'' signals consist of a superposition of a ``noise'' signal and a signal or signals of interest. For example, the signal at the bottom of Figure 19 shows a superposition of slow variations of large magnitude as well as faster variations of smaller magnitude. Let us assume that the slower, larger signal is our signal of interest. We could try using a high pass filter to eliminate the smaller, faster signal. However, if we are only interested in knowing when and for how long our signal of interest is above some threshold, we could use transistors to produce a circuit with an output voltage that is high or ``on'' when its input signal is above a ``turn on'' threshold and low or ``off'' otherwise. This circuit would produce several very short output pulses due to noise fluctuations as the signal crossed the threshold. If we refine the design so that the output only swings low after the signal crosses a second lower ``turn off'' threshold, we limit the sensitivity of the circuit to noise. In order for this idea to work, the difference between our ``turn on'' and ``turn off'' voltage thresholds should be somewhat larger than the peak to peak magnitude of the noise as shown in Figure 19.
Figure 19: A ``noisy'' input signal is shown below the desired output - high or ``on'' when the input signal has passed a ``turn on'' threshold and has not yet fallen below a lower ``turn off'' threshold. The two thresholds are arranged to prevent the circuit from responding to fluctuations due to noise.
\includegraphics{lab3-schmittgr.eps}
The device described above is known as a Schmitt trigger. It is an example of a class of devices called bistable multivibrators or flip flops. These devices, because they have two possible output states dependent on the history of the input signal have (at least short term) memory.

Design considerations

Figure 20: Nonlinear two state amplifier with different ``on'' and ``off'' input thresholds called a Schmitt trigger.
\includegraphics{lab3-schmitt.eps}
The circuit of Figure 20 is a Schmitt trigger circuit. The two transistors $Q_1$ and $Q_2$ are the key to the bistable behavior of the circuit. With the circuit in the ``on'' state, $Q_1$ is active ( $V_{BE1} \approx 0.7$ V) while $Q_2$ is inactive ($V_{BE2} < 0.7$ V). In the ``off'' state, they trade roles. Neither transistor is saturated. It is important to note that these are not conclusions one can draw looking Figure 20 in the absence of resistance values. Instead, these are assertions that get us started in understanding the behavior of the circuit. It is further helpful to start at the left of Figure 19 and think through the generation of an output pulse as follows.
  • $V_{in}$ low, $V_{out}$ low (trigger ``off'')
    The trigger is ``off'' in this state. We start with the assumption that in this state, $Q_1$ is inactive and $Q_2$ is active. If we mentally remove $Q_1$ from the circuit as depicted in Figure 21(a), we have what looks like a somewhat tangled common emitter amplifier. The base voltage of $Q_2$ is set by the voltage divider consisting of $R_1 + R_3$ and $R_4$. If $Q_2$ is active but not saturated, $V_{BE2} = V_{B2} - V_{E2} \approx 0.7$ V, or
    \begin{displaymath} \left( \frac{R_4}{R_1 + R_3 + R_4} \right) V_{cc} - I_{C2} R_E \approx 0.7~\textrm{V} \end{displaymath} (9)
    where $I_{C2}$ is the collector current of $Q_2$. For our purposes, we can and do consider the collector and emitter currents to be equal. Further, the output voltage corresponding to the ``off'' state is given by
    \begin{displaymath} V_{off} = V_{cc} - I_{C2} R_2. \end{displaymath} (10)

    Figure 21: Schmitt trigger in the (a) ``off'' ($Q_1$ inactive) and (b) ``on'' ($Q_2$ inactive) states.
    (a) \scalebox{0.7}{ \includegraphics{lab3-schmittoff.eps} } (b) \scalebox{0.7}{ \includegraphics{lab3-schmitton.eps} }
  • $V_{in}$ rising, $V_{out}$ low (trigger ``off'')
    Noting that the emitters of $Q_1$ and $Q_2$ are tied together, we conclude that the base and base emitter voltages at which they activate are equal. We already know the voltage of the base of $Q_2$ when the circuit is in the ``off'' state. Hence, we have the input threshold for turning on $Q_1$ and triggering the transition to the ``on'' state,
    \begin{displaymath} V_{turn~on} = \left( \frac{R_4}{R_1 + R_3 + R_4} \right) V_{cc}. \end{displaymath} (11)
  • $V_{in}$ high, $V_{out}$ high (trigger ``on'')
    The trigger is in the ``on'' state (see Figure 21). Once $Q_2$ is inactive, $I_{C2} = 0$, and there is no voltage drop across $R_2$. We can conclude that
    \begin{displaymath} V_{on} = 5~\textrm{V}. \end{displaymath} (12)
  • $V_{in}$ falling, $V_{out}$ high (trigger ``on'')
    In this state, there are three unique currents $I_1$, $I_2$, and $I_{C1}$ flowing in the circuit as shown in Figure 21(b). The node rule gives
    \begin{displaymath} I_1 = I_{C1} + I_2. \end{displaymath} (13)
    We can further observe, via the loop rule, that
    \begin{displaymath} I_1 R_1 + I_2 (R_3 + R_4) = V_{cc}. \end{displaymath} (14)
    The key to finding the ``turn off'' threshold input voltage $V_{turn~off}$ is recognizing that the base emitter voltages of $Q_1$ and $Q_2$ are both $\approx 0.7$ V when $Q_1$ is deactivating and $Q_2$ is activating. This yields a third constraint
    \begin{displaymath} V_{turn~off} \approx I_{C1} R_E + 0.7 \approx I_2 R_4 \end{displaymath} (15)
    which, together with Equations 13 and 14 allows us to eliminate the three unknown currents. In this way, it can be shown that
    \begin{displaymath} V_{turn~off} \approx \frac{R_4 (V_{cc} + \frac{R_1}{R_E}~0.7~\textrm{V})} {R_1 + R_3 + R_4 + \frac{R_1 R_4}{R_E}}. \end{displaymath} (16)

Assignment


  1. Use Spice to predict the behavior of the circuit assuming $R_1 = 4.7$ k$\Omega $, $R_2 = 3.9$ k$\Omega $, $R_3 = 2.2$ k$\Omega $, $R_4 = 5.6$ k$\Omega $, and $R_E = 2.7$ k$\Omega $. You will need to use two separate DC sweep analyses (one from 0 V up to 5 V, and one from 5 V down to 0 V) instead of a transient analysis.8Produce a graph of $V_{out}$ vs. $V_{in}$. Make note of the values of $V_{turn~on}$, $V_{turn~off}$, $V_{on}$, and $V_{off}$ that Spice predicts.
  2. Build the circuit using the resistance values you used in your Spice simulation, and use the X-Y mode of the oscilloscope to produce a graph of $V_{out}$ vs. $V_{in}$ for comparison with your Spice calculation. Measure actual values of $V_{turn~on}$, $V_{turn~off}$, $V_{on}$, and $V_{off}$. How well do Spice and experiment compare?
  3. Use Equations 9-11 to show that
    \begin{displaymath} V_{off} = V_{cc} - \frac{R_2}{R_E}(V_{turn~on} - 0.7~\textrm{V}). \end{displaymath} (17)
  4. Fill in the missing steps leading from Equations 13-15 to Equation 16 in the design discussion above. Compare theoretical predictions of $V_{turn~on}$, $V_{turn~off}$, $V_{on}$, and $V_{off}$ with your measurements and Spice results.
  5. What are the theoretical input and output impedances of the circuit in terms of the resistances $R_1$, $R_2$, $R_3$, $R_4$, and $R_E$? The voltage specifications of your Schmitt trigger (the values of $V_{turn~on}$, $V_{turn~off}$, $V_{on}$, and $V_{off}$ you report) actually depend on the input and output impedances of your trigger, the input impedance of the load, and output impedance of the driving circuit. If you would like your circuit to adhere to these specifications to within 1%, estimate (a) the upper limit on output impedances of circuits used to generate input signals for your Schmitt trigger, and (b) the lower limit on input impedances of loads driven by your Schmitt trigger. Do the function generator and oscilloscope you used to evaluate the circuit fall within these limits?
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